User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 638
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Bit Name Reset Access Description
Value Mode Description
3 PRSCH3 PRS Channel 3 selected as input
4 PRSCH4 PRS Channel 4 selected as input
5 PRSCH5 PRS Channel 5 selected as input
6 PRSCH6 PRS Channel 6 selected as input
7 PRSCH7 PRS Channel 7 selected as input
8 PRSCH8 PRS Channel 8 selected as input
9 PRSCH9 PRS Channel 9 selected as input
10 PRSCH10 PRS Channel 10 selected as input
11 PRSCH11 PRS Channel 11 selected as input
9 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
8 INPUT 0 RW
Select input to the LESENSE decoder
Value Mode Description
0 SENSORSTATE The SENSORSTATE register is used as input to the decoder.
1 PRS PRS channels are used as input to the decoder.
7 PRSCNT 0 RW Enable count mode on decoder PRS channels 0 and 1
When set, decoder PRS0 and PRS1 will be used to produce output which can be used by a PCNT to count up or down.
6 HYSTIRQ 0 RW Enable decoder hysteresis on interrupt requests
When set, hysteresis is enabled in the decoder, suppressing interrupt requests.
5 HYSTPRS2 0 RW Enable decoder hysteresis on PRS2 output
When set, hysteresis is enabled in the decoder, suppressing changes on PRS channel 2
4 HYSTPRS1 0 RW Enable decoder hysteresis on PRS1 output
When set, hysteresis is enabled in the decoder, suppressing changes on PRS channel 1
3 HYSTPRS0 0 RW Enable decoder hysteresis on PRS0 output
When set, hysteresis is enabled in the decoder, suppressing changes on PRS channel 0
2 INTMAP 0 RW Enable decoder to channel interrupt mapping
When set, a transition from state x in the decoder will set interrupt flag CHx
1 ERRCHK 0 RW Enable check of current state
When set, the decoder checks the current state in addition to the states defined in TCONF
0 DISABLE 0 RW Disable the decoder
When set, the decoder is disabled. When disabled the decoder will keep its current state
25.5.5 LESENSE_BIASCTRL - Bias Control Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 20) .
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
Access
RW
Name
BIASMODE
Bit Name Reset Access Description
31:2 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)