User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 636
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Bit Name Reset Access Description
Value Mode Description
1 PIN DAC CH1 output to pin enabled, output to ADC and ACMP disabled
2 ADCACMP DAC CH1 output to pin disabled, output to ADC and ACMP enabled
3 PINADCACMP DAC CH1 output to pin, ADC, and ACMP enabled.
7:6 DACCH0OUT 0x0 RW DAC channel 0 output mode
Value Mode Description
0 DISABLE DAC CH0 output to pin and ACMP/ADC disabled
1 PIN DAC CH0 output to pin enabled, output to ADC and ACMP disabled
2 ADCACMP DAC CH0 output to pin disabled, output to ADC and ACMP enabled
3 PINADCACMP DAC CH0 output to pin, ADC, and ACMP enabled.
5:4 DACCH1CONV 0x0 RW DAC channel 1 conversion mode
Value Mode Description
0 DISABLE LESENSE does not control DAC CH1.
1 CONTINUOUS DAC channel 1 is driven in continuous mode.
2 SAMPLEHOLD DAC channel 1 is driven in sample hold mode.
3 SAMPLEOFF DAC channel 1 is driven in sample off mode.
3:2 DACCH0CONV 0x0 RW DAC channel 0 conversion mode
Value Mode Description
0 DISABLE LESENSE does not control DAC CH0.
1 CONTINUOUS DAC channel 0 is driven in continuous mode.
2 SAMPLEHOLD DAC channel 0 is driven in sample hold mode.
3 SAMPLEOFF DAC channel 0 is driven in sample off mode.
1 DACCH1DATA 0 RW DAC CH1 data selection.
Configure DAC data control.
Value Mode Description
0 DACDATA DAC data is defined by CH1DATA in the DAC interface.
1 ACMPTHRES DAC data is defined by ACMPTHRES in CHx_INTERACT.
0 DACCH0DATA 0 RW DAC CH0 data selection.
Value Mode Description
0 DACDATA DAC data is defined by CH0DATA in the DAC interface.
1 ACMPTHRES DAC data is defined by ACMPTHRES in CHx_INTERACT.
25.5.4 LESENSE_DECCTRL - Decoder control Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 20) .
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0x0
0x0
0
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
PRSSEL3
PRSSEL2
PRSSEL1
PRSSEL0
INPUT
PRSCNT
HYSTIRQ
HYSTPRS2
HYSTPRS1
HYSTPRS0
INTMAP
ERRCHK
DISABLE