User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 633
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Bit Name Reset Access Description
Value Mode Description
0 ALTEX Alternative excitation is mapped to the LES_ALTEX pins.
1 ACMP Alternative excitation is mapped to the pins of the other ACMP.
10 ACMP1INV 0 RW Invert analog comparator 1 output
9 ACMP0INV 0 RW Invert analog comparator 0 output
8 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
7:6 SCANCONF 0x0 RW Select scan configuration
These bits control which CHx_CONF registers to be used.
Value Mode Description
0 DIRMAP The channel configuration register registers used are directly mapped to the channel
number.
1 INVMAP The channel configuration register registers used are CH
X+8
_CONF for channels 0-7
and CH
X-8
_CONF for channels 8-15.
2 TOGGLE The channel configuration register registers used toggles between CH
X
_CONF and
CH
X+8
_CONF when channel x triggers
3 DECDEF The decoder state defines the CONF registers to be used.
5:2 PRSSEL 0x0 RW Scan start PRS select
Select PRS source for scan start if SCANMODE is set to PRS.
Value Mode Description
0 PRSCH0 PRS Channel 0 selected as input
1 PRSCH1 PRS Channel 1 selected as input
2 PRSCH2 PRS Channel 2 selected as input
3 PRSCH3 PRS Channel 3 selected as input
4 PRSCH4 PRS Channel 4 selected as input
5 PRSCH5 PRS Channel 5 selected as input
6 PRSCH6 PRS Channel 6 selected as input
7 PRSCH7 PRS Channel 7 selected as input
8 PRSCH8 PRS Channel 8 selected as input
9 PRSCH9 PRS Channel 9 selected as input
10 PRSCH10 PRS Channel 10 selected as input
11 PRSCH11 PRS Channel 11 selected as input
1:0 SCANMODE 0x0 RW Configure scan mode
These bits control how the scan frequency is decided
Value Mode Description
0 PERIODIC A new scan is started each time the period counter overflows
1 ONESHOT A single scan is performed when START in CMD is set
2 PRS Pulse on PRS channel
25.5.2 LESENSE_TIMCTRL - Timing Control Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 20) .