User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 613
www.energymicro.com
Bit Name Reset Access Description
Value Mode Description
1 LOC1 Location 1
2 LOC2 Location 2
3 LOC3 Location 3
7:0 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
24.5.12 PCNTn_FREEZE - Freeze Register
Offset Bit Position
0x02C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
RW
Name
REGFREEZE
Bit Name Reset Access Description
31:1 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
0 REGFREEZE 0 RW Register Update Freeze
When set, the update of the PCNT clock domain is postponed until this bit is cleared. Use this bit to update several registers
simultaneously.
Value Mode Description
0 UPDATE Each write access to a PCNT register is updated into the Low Frequency domain as
soon as possible.
1 FREEZE The PCNT clock domain is not updated with the new written value.
24.5.13 PCNTn_SYNCBUSY - Synchronization Busy Register
Offset Bit Position
0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
Access
R
R
R
Name
TOPB
CMD
CTRL
Bit Name Reset Access Description
31:3 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2 TOPB 0 R PCNTn_TOPB Register Busy
Set when the value written to PCNTn_TOPB is being synchronized.
1 CMD 0 R PCNTn_CMD Register Busy
Set when the value written to PCNTn_CMD is being synchronized.
0 CTRL 0 R PCNTn_CTRL Register Busy
Set when the value written to PCNTn_CTRL is being synchronized.