User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 607
www.energymicro.com
24.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 PCNTn_CTRL RW Control Register
0x004 PCNTn_CMD W1 Command Register
0x008 PCNTn_STATUS R Status Register
0x00C PCNTn_CNT R Counter Value Register
0x010 PCNTn_TOP R Top Value Register
0x014 PCNTn_TOPB RW Top Value Buffer Register
0x018 PCNTn_IF R Interrupt Flag Register
0x01C PCNTn_IFS W1 Interrupt Flag Set Register
0x020 PCNTn_IFC W1 Interrupt Flag Clear Register
0x024 PCNTn_IEN RW Interrupt Enable Register
0x028 PCNTn_ROUTE RW I/O Routing Register
0x02C PCNTn_FREEZE RW Freeze Register
0x030 PCNTn_SYNCBUSY R Synchronization Busy Register
0x038 PCNTn_AUXCNT RWH Auxillary Counter Value Register
0x03C PCNTn_INPUT RW PCNT Input Register
24.5 Register Description
24.5.1 PCNTn_CTRL - Control Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 20) .
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0
0
0
0
0
0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
AUXCNTEV
CNTEV
S1CDIR
HYST
RSTEN
FILT
EDGE
CNTDIR
MODE
Bit Name Reset Access Description
31:16 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
15:14 AUXCNTEV 0x0 RW Controls when the auxillary counter counts
Selects whether the auxillary counter responds to up-count events, down-count events or both
Value Mode Description
0 NONE Never counts
1 UP Counts up on up-count events
2 DOWN Counts up on down-count events
3 BOTH Counts up on both up-count and down-count events
13:12 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
11:10 CNTEV 0x0 RW Controls when the counter counts
Selects whether the regular counter responds to up-count events, down-count events or both