User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 599
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Bit Name Reset Access Description
2 UF 0 RW Underflow Interrupt Enable
Set to enable interrupt on the UF interrupt flag.
1 COMP1 0 RW Compare Match 1 Interrupt Enable
Set to enable interrupt on the COMP1 interrupt flag.
0 COMP0 0 RW Compare Match 0 Interrupt Enable
Set to enable interrupt on the COMP0 interrupt flag.
23.5.13 LETIMERn_FREEZE - Freeze Register
Offset Bit Position
0x030
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
Reset
0
Access
RW
Name
REGFREEZE
Bit Name Reset Access Description
31:1 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
0 REGFREEZE 0 RW Register Update Freeze
With the immediate write synchronization scheme the REGFREEZE register is no longer used.
Value Mode Description
0 UPDATE Each write access to a LETIMER register is updated into the Low Frequency domain
as soon as possible.
1 FREEZE The LETIMER is not updated with the new written value.
23.5.14 LETIMERn_SYNCBUSY - Synchronization Busy Register
Offset Bit Position
0x034
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
Reset
0 0 0 0 0 0
Access
R R R R R R
Name
REP1 REP0
COMP1 COMP0
CMD
CTRL
Bit Name Reset Access Description
31:6 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
5 REP1 0 R LETIMERn_REP1 Register Busy
Set when the value written to LETIMERn_REP1 is being synchronized.
4 REP0 0 R LETIMERn_REP0 Register Busy
Set when the value written to LETIMERn_REP0 is being synchronized.
3 COMP1 0 R LETIMERn_COMP1 Register Busy
Set when the value written to LETIMERn_COMP1 is being synchronized.
2 COMP0 0 R LETIMERn_COMP0 Register Busy