User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 580
www.energymicro.com
• Repeat done
• Optionally runs during debug
23.3 Functional Description
An overview of the LETIMER module is shown in Figure 23.1 (p. 580) . The LETIMER is a
16-bit down-counter with two compare registers, LETIMERn_COMP0 and LETIMERn_COMP1. The
LETIMERn_COMP0 register can optionally act as a top value for the counter. The repeat counter
LETIMERn_REP0 allows the timer to count a specified number of times before it stops. Both the
LETIMERn_COMP0 and LETIMERn_REP0 registers can be double buffered by the LETIMERn_COMP1
and LETIMERn_REP1 registers to allow continuous operation. The timer can generate a single pin
output, or two linked outputs.
Figure 23.1. LETIMER Overview
Peripheral bus
= 0
COMP1
(Top Buffer)
COMP0
(Top)
CNT (Counter)
REP0
(Repeat)
REP1
(Repeat Buffer)
= 1
LETIMER Control
and Status
Reload
Update
Update
Stop
0
LFACLK
LETIMERn
Start
RTC event
SW
pin
ctrl
LETn_O0
Pulse
Control
Underflow
(UF interrupt flag)
REP0 Zero
(REP0 interrupt flag)
Buffer
Written
Repeat
load logic
pin
ctrl
LETn_O1
Pulse
Control
Top load
logic
= 1
REP1 Zero
(REP1 interrupt flag)
=
=
COMP1 Match
(COMP1 interrupt flag)
COMP0 Match
(COMP0 interrupt flag)
23.3.1 Timer
The timer is started by setting command bit START in LETIMERn_CMD, and stopped by setting the
STOP command bit in the same register. RUNNING in LETIMERn_STATUS is set as long as the timer is
running. The timer can also be started on external signals, such as a compare match from the Real Time
Counter. If START and STOP are set at the same time, STOP has priority, and the timer will be stopped.
The timer value can be read using the LETIMERn_CNT register. The value cannot be written, but it
can be cleared by setting the CLEAR command bit in LETIMERn_CMD. If the CLEAR and START
commands are issued at the same time, the timer will be cleared, then start counting at the top value.
23.3.2 Compare Registers
The LETIMER has two compare match registers, LETIMERn_COMP0 and LETIMERn_COMP1.
Each of these compare registers are capable of generating an interrupt when the counter value