User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 570
www.energymicro.com
Bit Name Reset Access Description
Value Mode Description
1 LFRCO LFRCO selected as BURTC clock source.
2 LFXO LFXO selected as BURTC clock source.
3 ULFRCO ULFRCO selected as BURTC clock source.
11 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
10:8 PRESC 0x0 RW Select BURTC prescaler factor
The BURTC will be prescaled by a factor of 2
PRESC
Value Mode Description
0 DIV1 No prescaling.
1 DIV2 Prescaling factor of 2
2 DIV4 Prescaling factor of 4
3 DIV8 Prescaling factor of 8
4 DIV16 Prescaling factor of 16
5 DIV32 Prescaling factor of 32
6 DIV64 Prescaling factor of 64
7 DIV128 Prescaling factor of 128
7:5 LPCOMP 0x0 RW Low power mode compare configuration
This bitfield configures which bits to be evaluated for compare match in low power mode.
Value Mode Description
0 IGN0LSB Do not ignore any bits for compare match evaluation.
1 IGN1LSB The LSB of the counter is ignored for compare match evaluation.
2 IGN2LSB The two LSBs of the counter are ignored for compare match evaluation.
3 IGN3LSB The three LSBs of the counter are ignored for compare match evaluation.
4 IGN4LSB The four LSBs of the counter are ignored for compare match evaluation.
5 IGN5LSB The five LSBs of the counter are ignored for compare match evaluation.
6 IGN6LSB The six LSBs of the counter are ignored for compare match evaluation.
7 IGN7LSB The seven LSBs of the counter are ignored for compare match evaluation.
4 COMP0TOP 0 RW Compare clear enable
When set, the counter wraps around when CNT equals COMP0
3 RSTEN 1 RW Enable BURTC reset
Reset the Backup RTC. Register values are not reset.
2 DEBUGRUN 0 RW Debug Mode Run Enable
Set this bit to keep the BURTC running during a debug halt.
Value Description
0 RTC is frozen in debug mode
1 RTC is running in debug mode
1:0 MODE 0x0 RW BURTC Enable
Configure in which energy modes the BURTC should keep running.
Value Mode Description
0 DISABLE The BURTC is disabled.
1 EM2EN The BURTC is in normal operating mode, operating in EM0-EM2. Oscillators must be
enabled in CMU for use.
2 EM3EN The BURTC is enabled in EM0-EM3. Will prevent CMU from disabling used oscillators
all the way down to EM3.
3 EM4EN The BURTC is enabled in EM0-EM4. Will prevent CMU from disabling used oscillators
all the way down to EM4.
22.5.2 BURTC_LPMODE - Low power mode configuration (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 20) .