User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 564
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Bit Name Reset Access Description
Enable interrupt on overflow
21.5.9 RTC_FREEZE - Freeze Register
Offset Bit Position
0x020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
RW
Name
REGFREEZE
Bit Name Reset Access Description
31:1 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
0 REGFREEZE 0 RW Register Update Freeze
When set, the update of the RTC is postponed until this bit is cleared. Use this bit to update several registers simultaneously.
Value Mode Description
0 UPDATE Each write access to an RTC register is updated into the Low Frequency domain as
soon as possible.
1 FREEZE The RTC is not updated with the new written value until the freeze bit is cleared.
21.5.10 RTC_SYNCBUSY - Synchronization Busy Register
Offset Bit Position
0x024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
Access
R
R
R
Name
COMP1
COMP0
CTRL
Bit Name Reset Access Description
31:3 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2 COMP1 0 R RTC_COMP1 Register Busy
Set when the value written to RTC_COMP1 is being synchronized.
1 COMP0 0 R RTC_COMP0 Register Busy
Set when the value written to RTC_COMP0 is being synchronized.
0 CTRL 0 R RTC_CTRL Register Busy
Set when the value written to RTC_CTRL is being synchronized.