User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 561
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21.5.2 RTC_CNT - Counter Value Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x000000
Access
RWH
Name
CNT
Bit Name Reset Access Description
31:24 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
23:0 CNT 0x000000 RWH Counter Value
Gives access to the counter value of the RTC.
21.5.3 RTC_COMP0 - Compare Value Register 0 (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 20) .
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x000000
Access
RW
Name
COMP0
Bit Name Reset Access Description
31:24 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
23:0 COMP0 0x000000 RW Compare Value 0
A compare match event occurs when CNT is equal to this value. This event sets the COMP0 interrupt flag, and can be used to start
the LETIMER. It is also available as a PRS signal.
21.5.4 RTC_COMP1 - Compare Value Register 1 (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 20) .