User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 560
www.energymicro.com
21.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 RTC_CTRL RW Control Register
0x004 RTC_CNT RWH Counter Value Register
0x008 RTC_COMP0 RW Compare Value Register 0
0x00C RTC_COMP1 RW Compare Value Register 1
0x010 RTC_IF R Interrupt Flag Register
0x014 RTC_IFS W1 Interrupt Flag Set Register
0x018 RTC_IFC W1 Interrupt Flag Clear Register
0x01C RTC_IEN RW Interrupt Enable Register
0x020 RTC_FREEZE RW Freeze Register
0x024 RTC_SYNCBUSY R Synchronization Busy Register
21.5 Register Description
21.5.1 RTC_CTRL - Control Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 20) .
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
Access
RW
RW
RW
Name
COMP0TOP
DEBUGRUN
EN
Bit Name Reset Access Description
31:3 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2 COMP0TOP 0 RW Compare Channel 0 is Top Value
When set, the counter is cleared in the clock cycle after a compare match with compare channel 0.
Value Mode Description
0 DISABLE The top value of the RTC is 16777215 (0xFFFFFF)
1 ENABLE The top value of the RTC is given by COMP0
1 DEBUGRUN 0 RW Debug Mode Run Enable
Set this bit to enable the RTC to keep running in debug
Value Description
0 RTC is frozen in debug mode
1 RTC is running in debug mode
0 EN 0 RW RTC Enable
When this bit is set, the RTC is enabled and counts up. When cleared, the counter register CNT is reset.