User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 551
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20.5.17 TIMERn_DTTIME - DTI Time Control Register
Offset Bit Position
0x074
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
0x00
0x0
Access
RW
RW
RW
Name
DTFALLT
DTRISET
DTPRESC
Bit Name Reset Access Description
31:22 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
21:16 DTFALLT 0x00 RW DTI Fall-time
Set time span for the falling edge.
Value Description
DTFALLT Fall time of DTFALLT+1 prescaled HFPERCLK cycles
15:14 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
13:8 DTRISET 0x00 RW DTI Rise-time
Set time span for the rising edge.
Value Description
DTRISET Rise time of DTRISET+1 prescaled HFPERCLK cycles
7:4 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
3:0 DTPRESC 0x0 RW DTI Prescaler Setting
Select prescaler for DTI.
Value Mode Description
0 DIV1 The HFPERCLK is undivided
1 DIV2 The HFPERCLK is divided by 2
2 DIV4 The HFPERCLK is divided by 4
3 DIV8 The HFPERCLK is divided by 8
4 DIV16 The HFPERCLK is divided by 16
5 DIV32 The HFPERCLK is divided by 32
6 DIV64 The HFPERCLK is divided by 64
7 DIV128 The HFPERCLK is divided by 128
8 DIV256 The HFPERCLK is divided by 256
9 DIV512 The HFPERCLK is divided by 512
10 DIV1024 The HFPERCLK is divided by 1024
20.5.18 TIMERn_DTFC - DTI Fault Configuration Register
Offset Bit Position
0x078
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
Name
DTLOCKUPFEN
DTDBGFEN
DTPRS1FEN
DTPRS0FEN
DTFA
DTPRS1FSEL
DTPRS0FSEL