User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 54
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Figure 8.2. Polling flowchart
Start polling
Is there
a channel
request ?
Are any
channel requests
using a high priority-
level ?
Start DMA transfer
N
o
Yes
Yes
Select channel that has
the lowest channel
number and is set to
high priority-level
Select channel that has
the lowest channel
number
No
8.4.2.3 DMA cycle types
The cycle_ctrl bits control how the controller performs a DMA cycle. You can set the cycle_ctrl bits as
Table 8.3 (p. 54) lists.
Table 8.3. DMA cycle types
cycle_ctrl Description
b000 Channel control data structure is invalid
b001 Basic DMA transfer
b010 Auto-request
b011 Ping-pong
b100 Memory scatter-gather using the primary data structure
b101 Memory scatter-gather using the alternate data structure
b110 Peripheral scatter-gather using the primary data structure
b111 Peripheral scatter-gather using the alternate data structure
Note
The cycle_ctrl bits are located in the channel_cfg memory location that Section 8.4.3.3 (p.
65) describes.
For all cycle types, the controller arbitrates after 2
R
DMA transfers. If you set a low-priority channel with
a large 2
R
value then it prevents all other channels from performing a DMA transfer, until the low-priority