User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 538
www.energymicro.com
20.5 Register Description
20.5.1 TIMERn_CTRL - Control Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0x0
0x0
0
0x0
0x0
0
0
0
0
0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RSSCOIST
ATI
PRESC
CLKSEL
X2CNT
FALLA
RISEA
DMACLRACT
DEBUGRUN
QDM
OSMEN
SYNC
MODE
Bit Name Reset Access Description
31:30 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
29 RSSCOIST 0 RW Reload-Start Sets Compare Ouptut initial State
When enabled, compare output is set to COIST value at Reload-Start event
28 ATI 0 RW Always Track Inputs
Enable ATI makes CCPOL always track the polarity of the inputs
27:24 PRESC 0x0 RW Prescaler Setting
These bits select the prescaling factor.
Value Mode Description
0 DIV1 The HFPERCLK is undivided
1 DIV2 The HFPERCLK is divided by 2
2 DIV4 The HFPERCLK is divided by 4
3 DIV8 The HFPERCLK is divided by 8
4 DIV16 The HFPERCLK is divided by 16
5 DIV32 The HFPERCLK is divided by 32
6 DIV64 The HFPERCLK is divided by 64
7 DIV128 The HFPERCLK is divided by 128
8 DIV256 The HFPERCLK is divided by 256
9 DIV512 The HFPERCLK is divided by 512
10 DIV1024 The HFPERCLK is divided by 1024
23:18 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
17:16 CLKSEL 0x0 RW Clock Source Select
These bits select the clock source for the timer.
Value Mode Description
0 PRESCHFPERCLK Prescaled HFPERCLK
1 CC1 Compare/Capture Channel 1 Input
2 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower
numbered neighbor Timer
15:14 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
13 X2CNT 0 RW 2x Count Mode
Enable 2x count mode
12 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
11:10 FALLA 0x0 RW Timer Falling Input Edge Action
These bits select the action taken in the counter when a falling edge occurs on the input.
Value Mode Description
0 NONE No action
1 START Start counter without reload