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2012-04-24 - Giant Gecko Family - d0053_Rev0.96 531
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20.3.2.7 Up/Down-count (Dual-slope) PWM
If the counter is set to up-down count and the Compare/Capture channel is put in PWM mode, dual
slope PWM output will be generated by Figure 20.20 (p. 531) .The resolution (in bits) is given by
Equation 20.9 (p. 531) .
Figure 20.20. TIMER Up/Down-count PWM Generation
0
TIMERn_TOP
TIMERn_CCx_CCV
TIMn_CCx
Overflow
Compare match
Buffer update
TIMER Up/Down-count PWM Resolution Equation
R
PWM
up/down
= log(TOP+1)/log(2) (20.9)
The PWM frequency is given by Equation 20.10 (p. 531) :
TIMER Up/Down-count PWM Frequency Equation
f
PWM
up/down
= f
HFPERCLK
/ ( 2^(PRESC+1) x TOP) (20.10)
The high duty cycle is given by Equation 20.11 (p. 531)
TIMER Up/Down-count Duty Cycle Equation
DS
up/down
= CCVx/TOP (20.11)
20.3.2.7.1 2x Count Mode
When the Timer is set in 2x mode, the TIMER will count up/down by two. This will in effect make any
odd Top value be rounded down to the closest even number. Similarly, any odd CC value will generate
a match on the closest lower even value as shown in Figure 20.21 (p. 531)
Figure 20.21. TIMER CC out in 2x mode
2 4 2 0 20
Clock
CC Out
4
2 4 2 0 20
4
Top = 5
CC = 1
Top = 5
CC = 2
The mode is enabled by setting the X2CNT field in TIMERn_CTRL register. The intended use of the
2x mode is to generate 2x PWM frequency when the Compare/Capture channel is put in PWM mode.
Since the PWM output is updated on both edges of the clock, frequency prescaling will result in incorrect
result in this mode. The PWM resolution (in bits) is then given by Equation 20.12 (p. 532) .