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2012-04-24 - Giant Gecko Family - d0053_Rev0.96 52
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and this determines the arbitration rate. For example, if R = 4 then the arbitration rate is 2
4
, that is, the
controller arbitrates every 16 DMA transfers.
Table 8.1 (p. 52) lists the arbitration rates.
Table 8.1. AHB bus transfer arbitration interval
R_power Arbitrate after x DMA transfers
b0000 x = 1
b0001 x = 2
b0010 x = 4
b0011 x = 8
b0100 x = 16
b0101 x = 32
b0110 x = 64
b0111 x = 128
b1000 x = 256
b1001 x = 512
b1010 - b1111 x = 1024
Note
You must take care not to assign a low-priority channel with a large R_power because this
prevents the controller from servicing high-priority requests, until it rearbitrates.
When N > 2
R
and is not an integer multiple of 2
R
then the controller always performs sequences of 2
R
transfers until N < 2
R
remain to be transferred. The controller performs the remaining N transfers at the
end of the DMA cycle.
You store the value of the R_power bits in the channel control data structure. See Section 8.4.3.3 (p.
65) for more information about the location of the R_power bits in the data structure.
8.4.2.2 Priority
When the controller arbitrates, it determines the next channel to service by using the following
information:
• the channel number
• the priority level, default or high, that is assigned to the channel.
You can configure each channel to use either the default priority level or a high priority level by setting
the DMA_CHPRIS register.
Channel number zero has the highest priority and as the channel number increases, the priority of a
channel decreases. Table 8.2 (p. 52) lists the DMA channel priority levels in descending order of
priority.
Table 8.2. DMA channel priority
Channel
number
Priority level
setting
Descending order of
channel priority
0 High Highest-priority DMA channel