User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 516
www.energymicro.com
Bit Name Reset Access Description
31:6 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
5 PULSEFILT 0 RW Pulse Filter
Enable a one-cycle pulse filter for pulse extender
Value Description
0 Filter is disabled. Pulses must be at least 2 cycles long for reliable detection.
1 Filter is enabled. Pulses must be at least 3 cycles long for reliable detection.
4 PULSEEN 0 RW Pulse Generator/Extender Enable
Filter LEUART output through pulse generator and the LEUART input through the pulse extender.
3:0 PULSEW 0x0 RW Pulse Width
Configure the pulse width of the pulse generator as a number of 32.768 kHz clock cycles.
19.5.17 LEUARTn_FREEZE - Freeze Register
Offset Bit Position
0x040
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
RW
Name
REGFREEZE
Bit Name Reset Access Description
31:1 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
0 REGFREEZE 0 RW Register Update Freeze
When set, the update of the LEUART is postponed until this bit is cleared. Use this bit to update several registers simultaneously.
Value Mode Description
0 UPDATE Each write access to a LEUART register is updated into the Low Frequency domain
as soon as possible.
1 FREEZE The LEUART is not updated with the new written value.
19.5.18 LEUARTn_SYNCBUSY - Synchronization Busy Register
Offset Bit Position
0x044
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Name
PULSECTRL
TXDATA
TXDATAX
SIGFRAME
STARTFRAME
CLKDIV
CMD
CTRL
Bit Name Reset Access Description
31:8 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
7 PULSECTRL 0 R LEUARTn_PULSECTRL Register Busy
Set when the value written to LEUARTn_PULSECTRL is being synchronized.
6 TXDATA 0 R LEUARTn_TXDATA Register Busy