User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 515
www.energymicro.com
19.5.15 LEUARTn_IEN - Interrupt Enable Register
Offset Bit Position
0x038
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
SIGF
STARTF
MPAF
FERR
PERR
TXOF
RXUF
RXOF
RXDATAV
TXBL
TXC
Bit Name Reset Access Description
31:11 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
10 SIGF 0 RW Signal Frame Interrupt Enable
Enable interrupt on signal frame.
9 STARTF 0 RW Start Frame Interrupt Enable
Enable interrupt on start frame.
8 MPAF 0 RW Multi-Processor Address Frame Interrupt Enable
Enable interrupt on multi-processor address frame.
7 FERR 0 RW Framing Error Interrupt Enable
Enable interrupt on framing error.
6 PERR 0 RW Parity Error Interrupt Enable
Enable interrupt on parity error.
5 TXOF 0 RW TX Overflow Interrupt Enable
Enable interrupt on TX overflow.
4 RXUF 0 RW RX Underflow Interrupt Enable
Enable interrupt on RX underflow.
3 RXOF 0 RW RX Overflow Interrupt Enable
Enable interrupt on RX overflow.
2 RXDATAV 0 RW RX Data Valid Interrupt Enable
Enable interrupt on RX data.
1 TXBL 0 RW TX Buffer Level Interrupt Enable
Enable interrupt on TX buffer level.
0 TXC 0 RW TX Complete Interrupt Enable
Enable interrupt on TX complete.
19.5.16 LEUARTn_PULSECTRL - Pulse Control Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 20) .
Offset Bit Position
0x03C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0x0
Access
RW
RW
RW
Name
PULSEFILT
PULSEEN
PULSEW