User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 512
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Bit Name Reset Access Description
Value Description
1 The transmitter is disabled, clearing TXENS after the frame has been transmitted
13 TXBREAK 0 W Transmit Data As Break
Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the value
of TXDATA.
Value Description
0 The specified number of stop-bits are transmitted
1 Instead of the ordinary stop-bits, 0 is transmitted to generate a break. A single stop-bit is generated after the break to
allow the receiver to detect the start of the next frame
12:9 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
8:0 TXDATA 0x000 W TX Data
Use this register to write data to the LEUART. If the transmitter is enabled, a transfer will be initiated at the first opportunity.
19.5.11 LEUARTn_TXDATA - Transmit Buffer Data Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 20) .
Offset Bit Position
0x028
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
W
Name
TXDATA
Bit Name Reset Access Description
31:8 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
7:0 TXDATA 0x00 W TX Data
This frame will be added to the transmit buffer. Only 8 LSB can be written using this register. 9th bit and control bits will be cleared.
19.5.12 LEUARTn_IF - Interrupt Flag Register
Offset Bit Position
0x02C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
Name
SIGF
STARTF
MPAF
FERR
PERR
TXOF
RXUF
RXOF
RXDATAV
TXBL
TXC
Bit Name Reset Access Description
31:11 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
10 SIGF 0 R Signal Frame Interrupt Flag
Set when a signal frame is detected.
9 STARTF 0 R Start Frame Interrupt Flag
Set when a start frame is detected.
8 MPAF 0 R Multi-Processor Address Frame Interrupt Flag