User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 505
www.energymicro.com
19.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 LEUARTn_CTRL RW Control Register
0x004 LEUARTn_CMD W1 Command Register
0x008 LEUARTn_STATUS R Status Register
0x00C LEUARTn_CLKDIV RW Clock Control Register
0x010 LEUARTn_STARTFRAME RW Start Frame Register
0x014 LEUARTn_SIGFRAME RW Signal Frame Register
0x018 LEUARTn_RXDATAX R Receive Buffer Data Extended Register
0x01C LEUARTn_RXDATA R Receive Buffer Data Register
0x020 LEUARTn_RXDATAXP R Receive Buffer Data Extended Peek Register
0x024 LEUARTn_TXDATAX W Transmit Buffer Data Extended Register
0x028 LEUARTn_TXDATA W Transmit Buffer Data Register
0x02C LEUARTn_IF R Interrupt Flag Register
0x030 LEUARTn_IFS W1 Interrupt Flag Set Register
0x034 LEUARTn_IFC W1 Interrupt Flag Clear Register
0x038 LEUARTn_IEN RW Interrupt Enable Register
0x03C LEUARTn_PULSECTRL RW Pulse Control Register
0x040 LEUARTn_FREEZE RW Freeze Register
0x044 LEUARTn_SYNCBUSY R Synchronization Busy Register
0x054 LEUARTn_ROUTE RW I/O Routing Register
0x0AC LEUARTn_INPUT RW LEUART Input Register
19.5 Register Description
19.5.1 LEUARTn_CTRL - Control Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 20) .
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
0
0
0
0
0
0
0
0
0x0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
TXDELAY
TXDMAWU
RXDMAWU
BIT8DV
MPAB
MPM
SFUBRX
LOOPBK
ERRSDMA
INV
STOPBITS
PARITY
DATABITS
AUTOTRI
Bit Name Reset Access Description
31:16 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
15:14 TXDELAY 0x0 RW TX Delay Transmission
Configurable delay before new transfers. Frames sent back-to-back are not delayed.
Value Mode Description
0 NONE Frames are transmitted immediately
1 SINGLE Transmission of new frames are delayed by a single baud period
2 DOUBLE Transmission of new frames are delayed by two baud periods