User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 484
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17.5.17 USARTn_IF - Interrupt Flag Register
Offset Bit Position
0x040
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
Name
CCF
SSM
MPAF
FERR
PERR
TXUF
TXOF
RXUF
RXOF
RXFULL
RXDATAV
TXBL
TXC
Bit Name Reset Access Description
31:13 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
12 CCF 0 R Collision Check Fail Interrupt Flag
Set when a collision check notices an error in the transmitted data.
11 SSM 0 R Slave-Select In Master Mode Interrupt Flag
Set when the device is selected as a slave when in master mode.
10 MPAF 0 R Multi-Processor Address Frame Interrupt Flag
Set when a multi-processor address frame is detected.
9 FERR 0 R Framing Error Interrupt Flag
Set when a frame with a framing error is received while RXBLOCK is cleared.
8 PERR 0 R Parity Error Interrupt Flag
Set when a frame with a parity error (asynchronous mode only) is received while RXBLOCK is cleared.
7 TXUF 0 R TX Underflow Interrupt Flag
Set when operating as a synchronous slave, no data is available in the transmit buffer when the master starts transmission of a
new frame.
6 TXOF 0 R TX Overflow Interrupt Flag
Set when a write is done to the transmit buffer while it is full. The data already in the transmit buffer is preserved.
5 RXUF 0 R RX Underflow Interrupt Flag
Set when trying to read from the receive buffer when it is empty.
4 RXOF 0 R RX Overflow Interrupt Flag
Set when data is incoming while the receive shift register is full. The data previously in the shift register is lost.
3 RXFULL 0 R RX Buffer Full Interrupt Flag
Set when the receive buffer becomes full.
2 RXDATAV 0 R RX Data Valid Interrupt Flag
Set when data becomes available in the receive buffer.
1 TXBL 1 R TX Buffer Level Interrupt Flag
Set when buffer becomes empty if TXBIL is set, or when buffer goes from full to half-full if TXBIL is cleared
0 TXC 0 R TX Complete Interrupt Flag
This interrupt is used after a transmission when both the TX buffer and shift register are empty.