User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 482
www.energymicro.com
Bit Name Reset Access Description
Set to disable transmitter and release data bus directly after transmission.
13 TXBREAK 0 W Transmit Data As Break
Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the value
of WDATA.
12 TXTRIAT 0 W Set TXTRI After Transmission
Set to tristate transmitter by setting TXTRI after transmission.
11 UBRXAT 0 W Unblock RX After Transmission
Set clear RXBLOCK after transmission, unblocking the receiver.
10:9 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
8:0 TXDATAX 0x000 W TX Data
Use this register to write data to the USART. If TXEN is set, a transfer will be initiated at the first opportunity.
17.5.14 USARTn_TXDATA - TX Buffer Data Register
Offset Bit Position
0x034
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
W
Name
TXDATA
Bit Name Reset Access Description
31:8 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
7:0 TXDATA 0x00 W TX Data
This frame will be added to TX buffer. Only 8 LSB can be written using this register. 9th bit and control bits will be cleared.
17.5.15 USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register
Offset Bit Position
0x038
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0x000
0
0
0
0
0
0x000
Access
W
W
W
W
W
W
W
W
W
W
W
W
Name
RXENAT1
TXDISAT1
TXBREAK1
TXTRIAT1
UBRXAT1
TXDATA1
RXENAT0
TXDISAT0
TXBREAK0
TXTRIAT0
UBRXAT0
TXDATA0
Bit Name Reset Access Description
31 RXENAT1 0 W Enable RX After Transmission
Set to enable reception after transmission.
30 TXDISAT1 0 W Clear TXEN After Transmission