User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 478
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Bit Name Reset Access Description
Set when the receiver is enabled.
17.5.6 USARTn_CLKDIV - Clock Control Register
Offset Bit Position
0x014
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
Reset
0x0000
Access
RW
Name
DIV
Bit Name Reset Access Description
31:21 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
20:6 DIV 0x0000 RW Fractional Clock Divider
Specifies the fractional clock divider for the USART.
5:0 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
17.5.7 USARTn_RXDATAX - RX Buffer Data Extended Register
Offset Bit Position
0x018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
Reset
0 0
0x000
Access
R R R
Name
FERR PERR
RXDATA
Bit Name Reset Access Description
31:16 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
15 FERR 0 R Data Framing Error
Set if data in buffer has a framing error. Can be the result of a break condition.
14 PERR 0 R Data Parity Error
Set if data in buffer has a parity error (asynchronous mode only).
13:9 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
8:0 RXDATA 0x000 R RX Data
Use this register to access data read from the USART. Buffer is cleared on read access.