User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 476
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Bit Name Reset Access Description
Select USART PRS trigger channel. The PRS signal can enable RX and/or TX, depending on the setting of RXTEN and TXTEN.
Value Mode Description
0 PRSCH0 PRS Channel 0 selected
1 PRSCH1 PRS Channel 1 selected
2 PRSCH2 PRS Channel 2 selected
3 PRSCH3 PRS Channel 3 selected
4 PRSCH4 PRS Channel 4 selected
5 PRSCH5 PRS Channel 5 selected
6 PRSCH6 PRS Channel 6 selected
7 PRSCH7 PRS Channel 7 selected
17.5.4 USARTn_CMD - Command Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
Name
CLEARRX
CLEARTX
TXTRIDIS
TXTRIEN
RXBLOCKDIS
RXBLOCKEN
MASTERDIS
MASTEREN
TXDIS
TXEN
RXDIS
RXEN
Bit Name Reset Access Description
31:12 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
11 CLEARRX 0 W1 Clear RX
Set to clear receive buffer and the RX shift register.
10 CLEARTX 0 W1 Clear TX
Set to clear transmit buffer and the TX shift register.
9 TXTRIDIS 0 W1 Transmitter Tristate Disable
Disables tristating of the transmitter output.
8 TXTRIEN 0 W1 Transmitter Tristate Enable
Tristates the transmitter output.
7 RXBLOCKDIS 0 W1 Receiver Block Disable
Set to clear RXBLOCK, resulting in all incoming frames being loaded into the receive buffer.
6 RXBLOCKEN 0 W1 Receiver Block Enable
Set to set RXBLOCK, resulting in all incoming frames being discarded.
5 MASTERDIS 0 W1 Master Disable
Set to disable master mode, clearing the MASTER status bit and putting the USART in slave mode.
4 MASTEREN 0 W1 Master Enable
Set to enable master mode, setting the MASTER status bit. Master mode should not be enabled while TXENS is set to 1. To enable
both master and TX mode, write MASTEREN before TXEN, or enable them both in the same write operation.
3 TXDIS 0 W1 Transmitter Disable
Set to disable transmission.
2 TXEN 0 W1 Transmitter Enable
Set to enable data transmission.
1 RXDIS 0 W1 Receiver Disable
Set to disable data reception. If a frame is under reception when the receiver is disabled, the incoming frame is discarded.