User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 471
www.energymicro.com
17.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 USARTn_CTRL RW Control Register
0x004 USARTn_FRAME RW USART Frame Format Register
0x008 USARTn_TRIGCTRL RW USART Trigger Control register
0x00C USARTn_CMD W1 Command Register
0x010 USARTn_STATUS R USART Status Register
0x014 USARTn_CLKDIV RW Clock Control Register
0x018 USARTn_RXDATAX R RX Buffer Data Extended Register
0x01C USARTn_RXDATA R RX Buffer Data Register
0x020 USARTn_RXDOUBLEX R RX Buffer Double Data Extended Register
0x024 USARTn_RXDOUBLE R RX FIFO Double Data Register
0x028 USARTn_RXDATAXP R RX Buffer Data Extended Peek Register
0x02C USARTn_RXDOUBLEXP R RX Buffer Double Data Extended Peek Register
0x030 USARTn_TXDATAX W TX Buffer Data Extended Register
0x034 USARTn_TXDATA W TX Buffer Data Register
0x038 USARTn_TXDOUBLEX W TX Buffer Double Data Extended Register
0x03C USARTn_TXDOUBLE W TX Buffer Double Data Register
0x040 USARTn_IF R Interrupt Flag Register
0x044 USARTn_IFS W1 Interrupt Flag Set Register
0x048 USARTn_IFC W1 Interrupt Flag Clear Register
0x04C USARTn_IEN RW Interrupt Enable Register
0x050 USARTn_IRCTRL RW IrDA Control Register
0x054 USARTn_ROUTE RW I/O Routing Register
0x058 USARTn_INPUT RW USART Input Register
0x05C USARTn_I2SCTRL RW I2S Control Register
17.5 Register Description
17.5.1 USARTn_CTRL - Control Register
Offset Bit Position
0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
Reset
0 0 0
0x0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x0
0 0 0 0 0
Access
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Name
MVDIS
AUTOTX
BYTESWAP
TXDELAY
ERRSTX ERRSRX
ERRSDMA
BIT8DV
SKIPPERRF SCRETRANS
SCMODE
AUTOTRI
AUTOCS
CSINV TXINV RXINV TXBIL
CSMA MSBF
CLKPHA CLKPOL
OVS
MPAB
MPM
CCEN
LOOPBK
SYNC
Bit Name Reset Access Description
31 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
30 MVDIS 0 RW Majority Vote Disable
Disable majority vote for 16x, 8x and 6x oversampling modes.
29 AUTOTX 0 RW Always Transmit When RX Not Full