User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 444
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Bit Name Reset Access Description
15 CLTO 0 RW Clock Low Interrupt Enable
Enable interrupt on clock low timeout.
14 BITO 0 RW Bus Idle Timeout Interrupt Enable
Enable interrupt on bus idle timeout.
13 RXUF 0 RW Receive Buffer Underflow Interrupt Enable
Enable interrupt on receive buffer underflow.
12 TXOF 0 RW Transmit Buffer Overflow Interrupt Enable
Enable interrupt on transmit buffer overflow.
11 BUSHOLD 0 RW Bus Held Interrupt Enable
Enable interrupt on bus-held.
10 BUSERR 0 RW Bus Error Interrupt Enable
Enable interrupt on bus error.
9 ARBLOST 0 RW Arbitration Lost Interrupt Enable
Enable interrupt on loss of arbitration.
8 MSTOP 0 RW MSTOP Interrupt Enable
Enable interrupt on MSTOP.
7 NACK 0 RW Not Acknowledge Received Interrupt Enable
Enable interrupt when not-acknowledge is received.
6 ACK 0 RW Acknowledge Received Interrupt Enable
Enable interrupt on acknowledge received.
5 RXDATAV 0 RW Receive Data Valid Interrupt Enable
Enable interrupt on receive buffer full.
4 TXBL 0 RW Transmit Buffer level Interrupt Enable
Enable interrupt on transmit buffer level.
3 TXC 0 RW Transfer Completed Interrupt Enable
Enable interrupt on transfer completed.
2 ADDR 0 RW Address Interrupt Enable
Enable interrupt on recognized address.
1 RSTART 0 RW Repeated START condition Interrupt Enable
Enable interrupt on transmitted or received repeated START condition.
0 START 0 RW START Condition Interrupt Enable
Enable interrupt on transmitted or received START condition.
16.5.15 I2Cn_ROUTE - I/O Routing Register
Offset Bit Position
0x038
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
Access
RW
RW
RW
Name
LOCATION
SCLPEN
SDAPEN
Bit Name Reset Access Description
31:11 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)