User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 426
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I2Cn_STATEDescription I2Cn_IF Required
interaction
Response
START START will be sent when bus becomes idle
None - Arbitration lost ARBLOST interrupt
flag
START START will be sent when bus becomes idle
16.3.8 Bus States
The I2Cn_STATE register can be used to determine which state the I
2
C module and the I2C bus are in
at a given time. The register consists of the STATE bit-field, which shows which state the I
2
C module is
at in any ongoing transmission, and a set of single-bits, which reveal the transmission mode, whether
the bus is busy or idle, and whether the bus is held by this I
2
C module waiting for a software response.
The possible values of the STATE field are summarized in Table 16.6 (p. 426) . When this field is
cleared, the I
2
C module is not a part of any ongoing transmission. The remaining status bits in the
I2Cn_STATE register are listed in Table 16.7 (p. 426) .
Table 16.6. I
2
C STATE Values
Mode Value Description
IDLE 0 No transmission is being performed by this module.
WAIT 1 Waiting for idle. Will send a start condition as soon as the bus is idle.
START 2 Start being transmitted
ADDR 3 Address being transmitted or has been received
ADDRACK 4 Address ACK/NACK being transmitted or received
DATA 5 Data being transmitted or received
DATAACK 6 Data ACK/NACK being transmitted or received
Table 16.7. I
2
C Transmission Status
Bit Description
BUSY Set whenever there is activity on the bus. Whether or not this module is
responsible for the activity cannot be determined by this byte.
MASTER Set when operating as a master. Cleared at all other times.
TRANSMITTER Set when operating as a transmitter; either a master transmitter or a slave
transmitter. Cleared at all other times
BUSHOLD Set when the bus is held by this I
2
C module because an action is required by
software.
NACK Only valid when bus is held and STATE is ADDRACK or DATAACK. In that case
it is set if a NACK was received. In all other cases, the bit is cleared.
Note
I2Cn_STATE reflects the internal state of the I
2
C module, and therefore only held constant
as long as the bus is held, i.e. as long as BUSHOLD in I2Cn_STATUS is set.
16.3.9 Slave Operation
The I
2
C module operates in master mode by default. To enable slave operation, i.e. to allow the device to
be addressed as an I
2
C slave, the SLAVE bit in I2Cn_CTRL must be set. In this case the slave operates
in a mixed mode, both capable of starting transmissions as a master, and being addressed as a slave.