User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 420
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After the address has been transmitted, a sequence of bytes can be read from or written to the slave,
depending on the value of the R/W bit (bit 0 in the address byte). If the bit was cleared, the master
has entered a master transmitter role, where it now transmits data to the slave. If the bit was set, it
has entered a master receiver role, where it now should receive data from the slave. In either case, an
unlimited number of bytes can be transferred in one direction during the transmission.
At the end of the transmission, the master either transmits a repeated START condition (Sr) if it wishes
to continue with another transfer, or transmits a STOP condition (P) if it wishes to release the bus.
16.3.7.1 Master State Machine
The master state machine is shown in Figure 16.10 (p. 420) . A master operation starts in the far
left of the state machine, and follows the solid lines through the state machine, ending the operation or
continuing with a new operation when arriving at the right side of the state machine.
Branches in the path through the state machine are the results of bus events and choices made by
software, either directly or indirectly. The dotted lines show where I
2
C-specific interrupt flags are set
along the path and the full-drawn circles show places where interaction may be required by software
to let the transmission proceed.
Figure 16.10. I
2
C Master State Machine
Waiting
for idle
Idle/busy
57
B3
9B
0
57
S
ADDR R A
N
ADDR W
A
N
DATA P
Sr
X Arb. lost 1
97 D7
DF
9F
A
N
A
N
DATA P
Sr
Arb. lost
ADDR R Arb. lost, ADDR match
ADDR W Arb. lost, ADDR match
ADDR X Arb. lost, no match 1
71
Master receiver
Master transmitter
Arbitration lost
Slave transmitter
Slave receiver
0
57
1
93
0/1
Bus state/event
Transmitted by self
Received from slave
START
condition
Interrupt flag set
Interaction required. Wait-
states inserted until manual
or automatic interaction has
been performed
Go to state
A
S P
N
Sr
ACK
STOP
condition
NACK
Repeated START condition
ADDR R
ADDR W
Slave address + read
(R/W bit set)
Slave address + write
(R/W bit cleared)
Bus state (STATE)
73
0P
Bus reset