User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 41
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Bit Name Reset Access Description
Value Mode Description
4 WS2 Two wait-states inserted for eatch fetch or read transfer. This mode is required for a
core frequency above 32 MHz
5 WS2SCBTP Two wait-state access with SCBTP enabled.
7.5.3 MSC_WRITECTRL - Write Control Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
Name
RWWEN
LPERASE
LPWRITE
WDOUBLE
IRQERASEABORT
WREN
Bit Name Reset Access Description
31:6 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
5 RWWEN 0 RW Read-While-Write Enable
When set, reads to the upper half of the flash can be done while writes/erases are being done in the lower half of the flash, and vice
versa. Reading from the same half as a flash write/erase will stall the access until the write/erase has completed.
4 LPERASE 0 RW Low-Power Erase
When set, the erase time doubles while halving the erase current
3 LPWRITE 0 RW Low-Power Erase
When set, write times might double while reducing current consumption
2 WDOUBLE 0 RW Write two words at a time
When set, two words are written to the flash at a time.
1 IRQERASEABORT 0 RW Abort Page Erase on Interrupt
When this bit is set to 1, any Cortex-M3 interrupt aborts any current page erase operation. Executing that interrupt vector from Flash
will halt the CPU.
0 WREN 0 RW Enable Write/Erase Controller
When this bit is set, the MSC write and erase functionality is enabled
7.5.4 MSC_WRITECMD - Write Command Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
W1
Name
CLEARWDATA
ERASEMAIN1
ERASEMAIN0
ERASEABORT
WRITETRIG
WRITEONCE
WRITEEND
ERASEPAGE
LADDRIM
Bit Name Reset Access Description
31:13 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)