User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 404
www.energymicro.com
Offset Bit Position
0x3CE00
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
R
R
RW
RW
RW
RW
Name
RESETAFTERSUSP
PHYSLEEP
RSTPDWNMODULE
PWRCLMP
GATEHCLK
STOPPCLK
Bit Name Reset Access Description
31:9 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
8 RESETAFTERSUSP 0 R Reset after suspend
When exiting EM2, this bit needs to be set in host mode before clamp is removed if the host needs to issue reset after suspend. If
this bit is not set, then the host issues resume after suspend. This bit is not applicable in device mode and when EM2 is not used.
7 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
6 PHYSLEEP 0 R PHY In Sleep
Indicates that the PHY is in Sleep State.
5:4 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
3 RSTPDWNMODULE 0 RW Reset Power-Down Modules
The application sets this bit to reset the part of the USB that is powered down during EM2. The application clears this bit to release
reset after an waking up from EM2 when the PHY clock is back at 48/6 MHz. Accessing core registers is possible only when this
bit is set to 0.
2 PWRCLMP 0 RW Power Clamp
The application sets this bit before the power is turned off to clamp the signals between the power-on modules and the power-off
modules of the USB core. The application clears the bit to disable the clamping.
1 GATEHCLK 0 RW Gate HCLK
The application sets this bit to gate the clock (HCLK) to modules other than the AHB Slave and Master and wakeup logic when the
USB is suspended or the session is not valid. The application clears this bit when the USB is resumed or a new session starts.
0 STOPPCLK 0 RW Stop PHY clock
The application sets this bit to stop the PHY clock when the USB is suspended, the session is not valid, or the device is disconnected.
The application clears this bit when the USB is resumed or a new session starts.
15.6.69 USB_FIFO0Dx - Device EP 0/Host Channel 0 FIFO
This register, available in both Host and Device modes, is used to read or write the FIFO space for
endpoint 0 or channel 0, in a given direction. If a host channel is of type IN, the FIFO can only be read
on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the channel.