User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 398
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Bit Name Reset Access Description
Value Mode Description
3 8B 8 bytes.
15.6.61 USB_DOEP0INT - Device OUT Endpoint 0 Interrupt Register
This register indicates the status of endpoint 0 with respect to USB- and AHB-related events. The
application must read this register when the OUT Endpoints Interrupt bit of the Core Interrupt register
(USB_GINTSTS.OEPINT) is set. Before the application can read this register, it must first read the
Device All Endpoints Interrupt (USB_DAINT) register to get the exact endpoint number for the Device
Endpoint Interrupt register. The application must clear the appropriate bit in this register to clear the
corresponding bits in the USB_DAINT and USB_GINTSTS registers.
Offset Bit Position
0x3CB08
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
Access
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
Name
NAKINTRPT
BBLEERR
PKTDRPSTS
BACK2BACKSETUP
OUTTKNEPDIS
SETUP
AHBERR
EPDISBLD
XFERCOMPL
Bit Name Reset Access Description
31:14 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
13 NAKINTRPT 0 RW1 NAK Interrupt
The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the
interrupt gets generated when a zero length packet is transmitted due to un-availability of data in the TXFifo.
12 BBLEERR 0 RW1 NAK Interrupt
The core generates this interrupt when babble is received for the endpoint.
11 PKTDRPSTS 0 RW1 Packet Drop Status
This bit indicates to the application that an ISO OUT packet has been dropped. This bit does not have an associated mask bit and
does not generate an interrupt.
10:7 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
6 BACK2BACKSETUP 0 RW1 Back-to-Back SETUP Packets Received
This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint.
5 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
4 OUTTKNEPDIS 0 RW1 OUT Token Received When Endpoint Disabled
Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for
which the OUT token was received.
3 SETUP 0 RW1 Setup Phase Done
Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for
the current control transfer. On this interrupt, the application can decode the received SETUP data packet.
2 AHBERR 0 RW1 AHB Error
This is generated only in DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding
endpoint DMA address register to get the error address.
1 EPDISBLD 0 RW1 Endpoint Disabled Interrupt
This bit indicates that the endpoint is disabled per the application's request.
0 XFERCOMPL 0 RW1 Transfer Completed Interrupt