User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 396
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Bit Name Reset Access Description
18:0 XFERSIZE 0x00000 RW Transfer Size
Indicates the transfer size in bytes. The core interrupts the application only after it has exhausted the transfer size amount of data.
The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core
decrements this field every time a packet from the external memory is written to the TxFIFO.
15.6.58 USB_DIEPx_DMAADDR - Device IN Endpoint x+1 DMA Address
Register
Offset Bit Position
0x3C934
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
DMAADDR
Bit Name Reset Access Description
31:0 DMAADDR 0xXXXXXXXX RW DMA Address
Holds the start address of the external memory for fetching endpoint data. For control endpoints, this field stores control OUT data
packets as well as SETUP transaction data packets. When more than three SETUP packets are received back-to-back, the SETUP
data packet in the memory is overwritten. This register is incremented on every AHB transaction. The application can give only a
DWORD-aligned address. The data for this register field is stored in RAM. Thus, the reset value is undefined (X).
15.6.59 USB_DIEPx_TXFSTS - Device IN Endpoint x+1 Transmit FIFO
Status Register
This read-only register contains the free space information for the Device IN endpoint TxFIFO.
Offset Bit Position
0x3C938
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0200
Access
R
Name
SPCAVAIL
Bit Name Reset Access Description
31:16 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
15:0 SPCAVAIL 0x0200 R TxFIFO Space Available
Indicates the amount of free space available in the Endpoint TxFIFO. Values are in terms of 32-bit words.