User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 392
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15.6.53 USB_DIEP0DMAADDR - Device IN Endpoint 0 DMA Address
Register
Offset Bit Position
0x3C914
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
DIEP0DMAADDR
Bit Name Reset Access Description
31:0 DIEP0DMAADDR 0xXXXXXXXX RW DMA Address
Holds the start address of the external memory for fetching endpoint data. For control endpoints, this field stores control OUT data
packets as well as SETUP transaction data packets. When more than three SETUP packets are received back-to-back, the SETUP
data packet in the memory is overwritten. This register is incremented on every AHB transaction. The application can give only a
DWORD-aligned address. The data for this register field is stored in RAM. Thus, the reset value is undefined (X).
15.6.54 USB_DIEP0TXFSTS - Device IN Endpoint 0 Transmit FIFO Status
Register
This read-only register contains the free space information for the Device IN endpoint 0 TxFIFO.
Offset Bit Position
0x3C918
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0200
Access
R
Name
SPCAVAIL
Bit Name Reset Access Description
31:16 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
15:0 SPCAVAIL 0x0200 R TxFIFO Space Available
Indicates the amount of free space available in the Endpoint TxFIFO. Values are in terms of 32-bit words.
15.6.55 USB_DIEPx_CTL - Device IN Endpoint x+1 Control Register
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.