User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 389
www.energymicro.com
Offset Bit Position
0x3C834
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
DIEPEMPMSK
Bit Name Reset Access Description
31:16 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
15:0 DIEPEMPMSK 0x0000 RW IN EP Tx FIFO Empty Interrupt Mask Bits
These bits acts as mask bits for USB_DIEP0INT.TXFEMP/USB_DIEPx_INT.TXFEMP interrupt. One bit per IN Endpoint: Bit 0 for
IN EP 0, bit 6 for IN EP 6.
15.6.50 USB_DIEP0CTL - Device IN Endpoint 0 Control Register
This section describes the Control IN Endpoint 0 Control register. Nonzero control endpoints use
registers for endpoints 1 - 6.
Offset Bit Position
0x3C900
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0x0
0
0x0
0
1
0x0
Access
RW1
RW1
W1
W1
RW
RW1
R
R
R
RW
Name
EPENA
EPDIS
SNAK
CNAK
TXFNUM
STALL
EPTYPE
NAKSTS
USBACTEP
MPS
Bit Name Reset Access Description
31 EPENA 0 RW1 Endpoint Enable
In DMA mode this bit indicates that data is ready to be transmitted on the endpoint. The core clears this bit before setting the following
interrupts on this endpoint: Endpoint Disabled, Transfer Completed.
30 EPDIS 0 RW1 Endpoint Disable
The application sets this bit to stop transmitting data on an endpoint, even before the transfer for that endpoint is complete. The
application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears this bit before
setting the Endpoint Disabled Interrupt. The application must set this bit only if Endpoint Enable is already set for this endpoint.
29:28 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
27 SNAK 0 W1 Set NAK
A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes
on an endpoint. The core can also set this bit for an endpoint after a SETUP packet is received on that endpoint.
26 CNAK 0 W1 Clear NAK
A write to this bit clears the NAK bit for the endpoint.
25:22 TXFNUM 0x0 RW TxFIFO Number
This value is set to the FIFO number that is assigned to IN Endpoint 0.
21 STALL 0 RW1 Handshake
The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global
Nonperiodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority.