User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 384
www.energymicro.com
status in the USB_DIEP0INT/USB_DIEPx_INT register can be masked by writing to the corresponding
bit in this register. Status bits are masked by default.
Offset Bit Position
0x3C810
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
Name
NAKMSK
TXFIFOUNDRNMSK
INEPNAKEFFMSK
INTKNTXFEMPMSK
TIMEOUTMSK
AHBERRMSK
EPDISBLDMSK
XFERCOMPLMSK
Bit Name Reset Access Description
31:14 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
13 NAKMSK 0 RW NAK interrupt Mask
Set to 1 to unmask NAK Interrupt.
12:9 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
8 TXFIFOUNDRNMSK 0 RW Fifo Underrun Mask
Set to 1 to unmask TXFIFOUNDRN Interrupt.
7 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
6 INEPNAKEFFMSK 0 RW IN Endpoint NAK Effective Mask
Set to 1 to unmask INEPNAKEFF Interrupt.
5 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
4 INTKNTXFEMPMSK 0 RW IN Token Received When TxFIFO Empty Mask
Set to 1 to unmask INTKNTXFEMP Interrupt.
3 TIMEOUTMSK 0 RW Timeout Condition Mask
Set to 1 to unmask Interrupt TIMEOUT. Applies to Non-isochronous endpoints.
2 AHBERRMSK 0 RW AHB Error Mask
Set to 1 to unmask AHBERR Interrupt.
1 EPDISBLDMSK 0 RW Endpoint Disabled Interrupt Mask
Set to 1 to unmask EPDISBLD Interrupt.
0 XFERCOMPLMSK 0 RW Transfer Completed Interrupt Mask
Set to 1 to unmask XFERCOMPL Interrupt.
15.6.44 USB_DOEPMSK - Device OUT Endpoint Common Interrupt Mask
Register
This register works with each of the Device OUT Endpoint Interrupt (USB_DOEP0INT/
USB_DOEPx_INT) registers for all endpoints to generate an interrupt per OUT endpoint. The OUT
endpoint interrupt for a specific status in the USB_DOEP0INT/USB_DOEPx_INT register can be masked
by writing into the corresponding bit in this register. Status bits are masked by default.