User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 383
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Bit Name Reset Access Description
The application uses this bit to signal the core to do a soft disconnect. As long as this bit is set, the host does not see that the device is
connected, and the device does not receive signals on the USB. The core stays in the disconnected state until the application clears
this bit. When suspended, the minimum duration for which the core must keep this bit set is 1 ms + 2.5 us. When IDLE or performing
transactions, the minimum duration for which the core must keep this bit set is 2.5 us.
0 RMTWKUPSIG 0 RW Remote Wakeup Signaling
When the application sets this bit, the core initiates remote signaling to wake up the USB host. The application must set this bit
to instruct the core to exit the Suspend state. As specified in the USB 2.0 specification, the application must clear this bit 1-15 ms
after setting it.
15.6.42 USB_DSTS - Device Status Register
This register indicates the status of the core with respect to USB-related events. It must be read on
interrupts from Device All Interrupts (USB_DAINT) register.
Offset Bit Position
0x3C808
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
0
0x1
0
Access
R
R
R
R
Name
SOFFN
ERRTICERR
ENUMSPD
SUSPSTS
Bit Name Reset Access Description
31:22 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
21:8 SOFFN 0x0000 R Frame Number of the Received SOF
This field contains a Frame number. This field may return a non zero value if read immediately after power on reset. In case the
register bits reads non zero immediately after power on reset it does not indicate that SOF has been received from the host. The
read value of this interrupt is valid only after a valid connection between host and device is established.
7:4 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
3 ERRTICERR 0 R Erratic Error
The core sets this bit to report any erratic errors (PHY error) Due to erratic errors, the core goes into Suspended state and an interrupt
is generated to the application with Early Suspend bit of the Core Interrupt register (USB_GINTSTS.ERLYSUSP). If the early suspend
is asserted due to an erratic error, the application can only perform a soft disconnect recover.
2:1 ENUMSPD 0x1 R Enumerated Speed
Indicates the speed at which the core has come up after speed detection through a chirp sequence.
Value Mode Description
2 LS Low speed (PHY clock is running at 6 MHz).
3 FS Full speed (PHY clock is running at 48 MHz).
0 SUSPSTS 0 R Suspend Status
In Device mode, this bit is set as long as a Suspend condition is detected on the USB. The core enters the Suspended state when
there is no activity on the bus for an extended period of time. The core comes out of the suspend when there is any activity on the
bus or when the application writes to the Remote Wakeup Signaling bit in the Device Control register (USB_DCTL.RMTWKUPSIG).
15.6.43 USB_DIEPMSK - Device IN Endpoint Common Interrupt Mask
Register
This register works with each of the Device IN Endpoint Interrupt (USB_DIEP0INT/USB_DIEPx_INT)
registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific