User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 381
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Bit Name Reset Access Description
31:0 DMAADDR 0xXXXXXXXX RW DMA Address
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must
be stored. This register is incremented on every AHB transaction. The data for this register field is stored in RAM. Thus, the reset
value is undefined (X).
15.6.40 USB_DCFG - Device Configuration Register
This register configures the core in Device mode after power-on or after certain control commands or
enumeration. Do not make changes to this register after initial programming.
Offset Bit Position
0x3C800
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x02
0x0
0x00
0
0
0x0
Access
RW
RW
RW
RW
RW
RW
Name
RESVALID
PERFRINT
DEVADDR
ENA32KHZSUSP
NZSTSOUTHSHK
DEVSPD
Bit Name Reset Access Description
31:26 RESVALID 0x02 RW Resume Validation Period
This field is effective only when USB_DCFG.ENA32KHZSUSP is set. It will control the resume period when the core resumes from
suspend. The core counts for RESVALID number of clock cycles to detect a valid resume when USB_DCFG.ENA32KHZSUSP is set.
25:13 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
12:11 PERFRINT 0x0 RW Periodic Frame Interval
Indicates the time within a frame at which the application must be notified using the End Of Periodic Frame Interrupt. This can be
used to determine if all the isochronous traffic for that frame is complete.
Value Mode Description
0 80PCNT 80% of the frame interval.
1 85PCNT 85% of the frame interval.
2 90PCNT 90% of the frame interval.
3 95PCNT 95% of the frame interval.
10:4 DEVADDR 0x00 RW Device Address
The application must program this field after every SetAddress control command.
3 ENA32KHZSUSP 0 RW Enable 32 KHz Suspend mode
When this bit is set, the core expects that the PHY clock during Suspend is switched from 48 MHz to 32 KHz.
2 NZSTSOUTHSHK 0 RW Non-Zero-Length Status OUT Handshake
The application can use this field to select the handshake the core sends on receiving a nonzero-length data packet during the OUT
transaction of a control transfer's Status stage. When set to 1 send a STALL handshake on a nonzero-length status OUT transaction
and do not send the received OUT packet to the application. When set to 0 send the received OUT packet to the application (zerolength
or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the Device Endpoint Control register.
1:0 DEVSPD 0x0 RW Device Speed
Indicates the speed at which the application requires the core to enumerate, or the maximum speed the application can support.
However, the actual bus speed is determined only after the chirp sequence is completed, and is based on the speed of the USB
host to which the core is connected.
Value Mode Description
2 LS Low speed (PHY clock is 6 MHz). If you select 6 MHz LS mode, you must do a soft
reset.
3 FS Full speed (PHY clock is 48 MHz).