User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 380
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15.6.38 USB_HCx_TSIZ - Host Channel x Transfer Size Register
Offset Bit Position
0x3C510
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x000
0x00000
Access
RW
RW
RW
Name
PID
PKTCNT
XFERSIZE
Bit Name Reset Access Description
31 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
30:29 PID 0x0 RW Packet ID
The application programs this field with the packet ID type to use for the initial transaction. The host maintains this field for the rest
of the transfer.
Value Mode Description
0 DATA0 DATA0 PID.
1 DATA2 DATA2 PID.
2 DATA1 DATA1 PID.
3 MDATA MDATA (non-control) / SETUP (control) PID.
28:19 PKTCNT 0x000 RW Packet Count
This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The
host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the
application is interrupted to indicate normal completion.
18:0 XFERSIZE 0x00000 RW Transfer Size
For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the
application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum
packet size for IN transactions (periodic and non-periodic).
15.6.39 USB_HCx_DMAADDR - Host Channel x DMA Address Register
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer
for IN/OUT transactions. The starting DMA address must be DWORD-aligned.
Offset Bit Position
0x3C514
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
DMAADDR