User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 379
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Bit Name Reset Access Description
0 XFERCOMPL 0 RW1 Transfer Completed
Transfer completed normally without any errors. This bit can be set only by the core and the application should write 1 to clear it.
15.6.37 USB_HCx_INTMSK - Host Channel x Interrupt Mask Register
This register reflects the mask for each channel status described in the USB_CHx_INT.
Offset Bit Position
0x3C50C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
DATATGLERRMSK
FRMOVRUNMSK
BBLERRMSK
XACTERRMSK
ACKMSK
NAKMSK
STALLMSK
AHBERRMSK
CHHLTDMSK
XFERCOMPLMSK
Bit Name Reset Access Description
31:11 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
10 DATATGLERRMSK 0 RW Data Toggle Error Mask
Set to unmask DATATGLERR interrupt.
9 FRMOVRUNMSK 0 RW Frame Overrun Mask
Set to unmask FRMOVRUN interrupt.
8 BBLERRMSK 0 RW Babble Error Mask
Set to unmask BBLERR interrupt.
7 XACTERRMSK 0 RW Transaction Error Mask
Set to unmask XACTERR interrupt.
6 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
5 ACKMSK 0 RW ACK Response Received/Transmitted Interrupt Mask
Set to unmask ACK interrupt.
4 NAKMSK 0 RW NAK Response Received Interrupt Mask
Set to unmask NAK interrupt.
3 STALLMSK 0 RW STALL Response Received Interrupt Mask
Set to unmask STALL interrupt.
2 AHBERRMSK 0 RW AHB Error Mask
Set to unmask AHBERR interrupt.
1 CHHLTDMSK 0 RW Channel Halted Mask
Set to unmask CHHLTD interrupt.
0 XFERCOMPLMSK 0 RW Transfer Completed Mask
Set to unmask XFERCOMPL interrupt.