User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 378
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Bit Name Reset Access Description
14:11 EPNUM 0x0 RW Endpoint Number
Indicates the endpoint number on the device serving as the data source or sink.
10:0 MPS 0x000 RW Maximum Packet Size
Indicates the maximum packet size of the associated endpoint.
15.6.36 USB_HCx_INT - Host Channel x Interrupt Register
This register indicates the status of a channel with respect to USB- and AHB-related events. The
application must read this register when the Host Channels Interrupt bit of the Core Interrupt register
(USB_GINTSTS.HCHINT) is set. Before the application can read this register, it must first read the Host
All Channels Interrupt (USB_HAINT) register to get the exact channel number for the Host Channel x
Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding
bits in the USB_HAINT and USB_GINTSTS registers.
Offset Bit Position
0x3C508
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
Access
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
Name
DATATGLERR
FRMOVRUN
BBLERR
XACTERR
ACK
NAK
STALL
AHBERR
CHHLTD
XFERCOMPL
Bit Name Reset Access Description
31:11 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
10 DATATGLERR 0 RW1 Data Toggle Error
This bit can be set only by the core and the application should write 1 to clear it.
9 FRMOVRUN 0 RW1 Frame Overrun
This bit can be set only by the core and the application should write 1 to clear it.
8 BBLERR 0 RW1 Babble Error
This bit can be set only by the core and the application should write 1 to clear it.
7 XACTERR 0 RW1 Transaction Error
Indicates one of the following errors occurred on the USB: CRC check failure, Timeout, Bit stuff error or False EOP. This bit can be
set only by the core and the application should write 1 to clear it.
6 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
5 ACK 0 RW1 ACK Response Received/Transmitted Interrupt
This bit can be set only by the core and the application should write 1 to clear it.
4 NAK 0 RW1 NAK Response Received Interrupt
This bit can be set only by the core and the application should write 1 to clear it.
3 STALL 0 RW1 STALL Response Received Interrupt
This bit can be set only by the core and the application should write 1 to clear it.
2 AHBERR 0 RW1 AHB Error
This is generated only in DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding
channel's DMA address register to get the error address.
1 CHHLTD 0 RW1 Channel Halted
In DMA mode this bit indicates the transfer completed abnormally either because of any USB transaction error or in response to
disable request by the application or because of a completed transfer.