User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 375
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Bit Name Reset Access Description
31:14 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
13:0 HAINT 0x0000 R Channel Interrupt for channel 0 - 13.
When the interrupt bit for a channel x set, one or more of the interrupt flags in the USB_HCx_INT are set.
15.6.33 USB_HAINTMSK - Host All Channels Interrupt Mask Register
The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt register to interrupt
the application when an event occurs on a channel. There is one interrupt mask bit per channel. Set
bits to unmask.
Offset Bit Position
0x3C418
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
HAINTMSK
Bit Name Reset Access Description
31:14 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
13:0 HAINTMSK 0x0000 RW Channel Interrupt Mask for channel 0 - 13
Set bit n to unmask channel n interrupts.
15.6.34 USB_HPRT - Host Port Control and Status Register
This register is available only in Host mode. This register holds USB port-related information such as USB
reset, enable, suspend, resume, connect status, and test mode for the port. Some bits in this register
can trigger an interrupt to the application through the Host Port Interrupt bit of the Core Interrupt register
(USB_GINTSTS.PRTINT). On a Port Interrupt, the application must read this register and clear the bit
that caused the interrupt. For the RW1 bits, the application must write a 1 to the bit to clear the interrupt.
Offset Bit Position
0x3C440
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0
0x0
0
0
0
0
0
0
0
0
0
Access
R
RW
RW
R
RW
RW1
RW
RW1
R
RW1
RW1
RW1
R
Name
PRTSPD
PRTTSTCTL
PRTPWR
PRTLNSTS
PRTRST
PRTSUSP
PRTRES
PRTOVRCURRCHNG
PRTOVRCURRACT
PRTENCHNG
PRTENA
PRTCONNDET
PRTCONNSTS
Bit Name Reset Access Description
31:19 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
18:17 PRTSPD 0x0 R Port Speed
Indicates the speed of the device attached to this port.