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...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 368
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Bit Name Reset Access Description
Indicates the amount of free space (locations) available in the Non-periodic Transmit Request Queue. This queue holds both IN and
OUT requests in Host mode. Device mode has only IN requests.
15:0 NPTXFSPCAVAIL 0x0200 R Non-periodic TxFIFO Space Available
Indicates the amount of free space available in the Non-periodic TxFIFO. Values are in terms of 32-bit words.
15.6.20 USB_GDFIFOCFG - Global DFIFO Configuration Register
Offset Bit Position
0x3C05C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x01F2
0x0200
Access
RW
RW
Name
EPINFOBASEADDR
GDFIFOCFG
Bit Name Reset Access Description
31:16 EPINFOBASEADDR 0x01F2 RW Endpoint Info Base Address
This field provides the start address of the EP info controller.
15:0 GDFIFOCFG 0x0200 RW DFIFO Config
This field is for dynamic programming of the DFIFO Size. This value takes effect only when the application programs a non zero
value to this register. The core does not have any corrective logic if the FIFO sizes are programmed incorrectly.
15.6.21 USB_HPTXFSIZ - Host Periodic Transmit FIFO Size Register
This register holds the size and the memory start address of the Periodic TxFIFO.
Offset Bit Position
0x3C100
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x200
0x400
Access
RW
RW
Name
PTXFSIZE
PTXFSTADDR
Bit Name Reset Access Description
31:26 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
25:16 PTXFSIZE 0x200 RW Host Periodic TxFIFO Depth
This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.
15:11 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
10:0 PTXFSTADDR 0x400 RW Host Periodic TxFIFO Start Address
This field contains the memory start address for Host Periodic TxFIFO.