User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 364
www.energymicro.com
Bit Name Reset Access Description
Set to 1 to unmask USBRST interrupt.
11 USBSUSPMSK 0 RW USB Suspend Mask (device only)
Set to 1 to unmask USBSUSP interrupt.
10 ERLYSUSPMSK 0 RW Early Suspend Mask (device only)
Set to 1 to unmask ERLYSUSP interrupt.
9:8 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
7 GOUTNAKEFFMSK 0 RW Global OUT NAK Effective Mask (device only)
Set to 1 to unmask GOUTNAKEFF interrupt.
6 GINNAKEFFMSK 0 RW Global Non-periodic IN NAK Effective Mask (device only)
Set to 1 to unmask GINNAKEFF interrupt.
5 NPTXFEMPMSK 0 RW Non-Periodic TxFIFO Empty Mask (host only)
Set to 1 to unmask NPTXFEMP interrupt.
4 RXFLVLMSK 0 RW Receive FIFO Non-Empty Mask (host and device)
Set to 1 to unmask RXFLVL interrupt.
3 SOFMSK 0 RW Start of Frame Mask (host and device)
Set to 1 to unmask SOF interrupt.
2 OTGINTMSK 0 RW OTG Interrupt Mask (host and device)
Set to 1 to unmask OTGINT interrupt.
1 MODEMISMSK 0 RW Mode Mismatch Interrupt Mask (host and device)
Set to 1 to unmask MODEMIS interrupt.
0 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
15.6.15 USB_GRXSTSR - Receive Status Debug Read Register
A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO.
The receive status contents must be interpreted differently in Host and Device modes. The core ignores
the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The
application must only pop the Receive Status FIFO when the Receive FIFO Non-Empty bit of the Core
Interrupt register (USB_GINTSTS.RXFLVL) is asserted.
Offset Bit Position
0x3C01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0x0
0x000
0x0
Access
R
R
R
R
R
Name
FN
PKTSTS
DPID
BCNT
CHEPNUM
Bit Name Reset Access Description
31:28 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
27:24 FN 0x0 R Frame Number (device only)
This is the least significant 4 bits of the Frame number in which the packet is received on the USB.
23:21 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
20:17 PKTSTS 0x0 R Packet Status (host or device)
Indicates the status of the received packet.