User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 356
www.energymicro.com
Offset Bit Position
0x3C004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
RW1
RW1
RW1
RW1
RW1
RW1
Name
DBNCEDONE
ADEVTOUTCHG
HSTNEGDET
HSTNEGSUCSTSCHNG
SESREQSUCSTSCHNG
SESENDDET
Bit Name Reset Access Description
31:20 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
19 DBNCEDONE 0 RW1 Debounce Done (host only)
The core sets this bit when the debounce is completed after the device connect. The application can start driving USB reset after
seeing this interrupt. This bit is only valid when the HNP Capable or SRP Capable bit is set in the Core USB Configuration register
(USB_GUSBCFG.HNPCAP or USB_GUSBCFG.SRPCAP, respectively). This bit can be set only by the core and the application
should write 1 to clear it.
18 ADEVTOUTCHG 0 RW1 A-Device Timeout Change (host and device)
The core sets this bit to indicate that the A-device has timed out while waiting for the B-device to connect. This bit can be set only
by the core and the application should write 1 to clear it.
17 HSTNEGDET 0 RW1 Host Negotiation Detected (host and device)
The core sets this bit when it detects a host negotiation request on the USB. This bit can be set only by the core and the application
should write 1 to clear it.
16:10 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
9 HSTNEGSUCSTSCHNG 0 RW1 Host Negotiation Success Status Change (host and device)
The core sets this bit on the success or failure of a USB host negotiation request. The application must read the Host Negotiation
Success bit of the OTG Control and Status register (USB_GOTGCTL.HSTNEGSCS) to check for success or failure. This bit can be
set only by the core and the application should write 1 to clear it.
8 SESREQSUCSTSCHNG 0 RW1 Session Request Success Status Change (host and device)
The core sets this bit on the success or failure of a session request. The application must read the Session Request Success bit
in the OTG Control and Status register (USB_GOTGCTL.SESREQSCS) to check for success or failure. This bit can be set only by
the core and the application should write 1 to clear it.
7:3 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2 SESENDDET 0 RW1 Session End Detected (host and device)
The core sets this bit when VBUS is in the range 0.8V - 2.0V. This bit can be set only by the core and the application should write
1 to clear it.
1:0 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
15.6.10 USB_GAHBCFG - AHB Configuration Register
This register can be used to configure the core after power-on or a change in mode. This register
mainly contains AHB system-related configuration parameters. Do not change this register after the
initial programming. The application must program this register before starting any transactions on either
the AHB or the USB.