User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 340
www.energymicro.com
• USB_GAHBCFG
• USB_GUSBCFG
• USB_GRXFSIZ
• USB_GNPTXFSIZ
• USB_DCFG
• USB_DIEPMSK
• USB_DOEPMSK
• USB_DIEPx_CTL
• USB_DIEPx_TSIZ
• USB_DIEPx_DMAADDR
• USB_PCGCCTL
• USB_DIEPTXFn
2. The application sets the Port Suspend bit in the Host Port CSR and the core drives a USB suspend.
3. The application clears the Port Power bit.
4. The application sets the Power Clamp bit in the Power and Clock Gating Control register, and the
core clamps the signals between the internal modules on different power rails.
5. The application sets the Reset to Power-Down Modules bit in the Power and Clock Gating Control
register.
6. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register, and the
core suspends the PHY, stopping the PHY clock.
7. Switch USBC clock to 32 kHz.
8. Enter EM2.
Host Mode Session Start (EM2 -> EM0)
Sequence of operations:
1. Exit EM2/Enter EM0).
2. Switch USBC clock back to 48 MHz.
3. The application clears the Stop PHY Clock bit.
4. The application clears the Power Clamp bit. The application clears the Reset to Power-Down Modules
bit.
5. The application programs CSRs and sets the Port Power bit to turn on VBUS.
6. The core detects the connection and drives the USB reset.
The core enters normal operating mode.
Host Mode Session End (EM0 -> EM2)
Sequence of operations:
1. Back up the essential registers of the core. Read and store the following core registers:
• USB_GINTMSK
• USB_GOTGCTL
• USB_GAHBCFG
• USB_GUSBCFG
• USB_GRXFSIZ
• USB_GNPTXFSIZ
• USB_DCFG
• USB_DCTL
• USB_DAINTMSK
• USB_DIEPMSK
• USB_DOEPMSK
• USB_DIEPx_CTL
• USB_DIEPx_TSIZ
• USB_DIEPx_DMAADDR
• USB_PCGCCTL
• USB_DIEPTXFn
2. The application sets the Port Suspend bit in the Host Port CSR and the core drives a USB suspend.
3. The application clears the Port Power bit.
4. The application sets the Power Clamp bit in the Power and Clock Gating Control register, and the
core clamps the signals between the internal modules on different power rails.
5. The application sets the Reset to Power-Down Modules bit in the Power and Clock Gating Control
register.