User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 302
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Figure 15.23. ISOC OUT Application Flow for Periodic Transfer Interrupt Feature
Not e:
1 . The (m icro-) fram e num be r and PID field are not updat ed for Periodic OUT
packet s
2 . In Periodic OUT transfers, any short packet results in an XferComplet e
Int errupt and disables the endpoint. The application must re enable the
endpoint with recalculated values of XferSize and PktCnt
3 . The applicat ion must reenable the endpoint aft er dropped packet s for
ISOC OU
START
Program the DMA address
START Address of t he Data M emory
Program Xfer_ size register
USB_DOEPx_TSIZ.XFERSIZE = XferSize Spanning across multiple Xfe rs
USB_DOEPx_TSIZ. .PKTCNT = Program PktCnt for m ult iple Xfers
Program the Global INT STS
GINTMSK.. INCOMPLPMSK = 0
// M ask IncompISOCOUT Interrupt
Intialize variables
Alloca t e a buffer in the Syst em Mem ory for m ultiple Xfers.
Buffer size must be a m ult iple of MaxPkt Size.
Program EP Ctrl register to start the xfer
USB_DOEPx_CTL . CNAK
= 1
USB_DOEPx_CTL .EPENA = 1
= 0
= 0
Wait for USB_DOEPx_INT. XFERCOMPL interrupt and report error if timeout expires
If USB_DOEPx_TSIZ.
XFERSIZE= = 0
If USB_DOEPx_INT.PKTDRPSTS
= =1
YES
End of Transfer
If USB_DOEPx_TSIZ.PKTCNT
= =0
YES
Return
NO
ISOC OUT PktDrop
YES
NO
If USB_DOEPx_TSIZ.
XFERSIZE != 0
Received Short Packet
YES
Received Short Packet
NO
Re- com pute XFERSIZE and
ERROR
NO
USB_DOEPx_CTL . SNAK
USB_DOEPx_CTL .EPDIS
USB_DOEPx_DMA =
PKTCNT
Internal Data Flow
1. The application must set the Transfer Size, Packets to be received in a frame and Packet Count Fields
in the endpoint-specific registers, clear the NAK bit, and enable the endpoint to receive the data.
2. When an isochronous OUT endpoint is enabled by setting the Endpoint Enable and clearing the NAK
bits, the Even/Odd frame will be ignored by the core.
3. Once the NAK bit is cleared, the core starts receiving data and writes it to the receive FIFO, as long
as there is space in the receive FIFO. For every data packet received on the USB, the data packet
and its status are written to the receive FIFO. Every packet (maximum packet size or short packet)
written to the receive FIFO decrements the Packet Count field for that endpoint by 1.
4. When the packet count becomes 0 or when a short packet is received on the endpoint, the NAK bit
for that endpoint is set. Once the NAK bit is set, the ISOC packets are ignored and not written to
the receive FIFO.
5. After the data is written to the receive FIFO, the core’s DMA engine, reads the data from the receive
FIFO and writes it to external memory, one packet at a time per endpoint.
6. At the end of every packet write on the AHB to external memory, the transfer size for the endpoint
is decremented by the size of the written packet.
7. The OUT Data Transfer Completed pattern for an OUT endpoint is written to the receive FIFO on
one of the following conditions.
• The transfer size is 0 and the packet count is 0