User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 233
www.energymicro.com
14.5.31 EBI_TFTTIMING - TFT Timing Register
Offset Bit Position
0x078
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
Reset
0x0 0x0
0x000 0x000
Access
RW RW RW RW
Name
TFTHOLD
TFTSETUP TFTSTART
DCLKPERIOD
Bit Name Reset Access Description
31:30 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
29:28 TFTHOLD 0x0 RW TFT Hold Time
Sets the number of internal clock cycles the RGB data is held after the active edge of EBI_DCLK.
27:26 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
25:24 TFTSETUP 0x0 RW TFT Setup Time
Sets the number of internal clock cycles the RGB data is driven before the active edge of EBI_DCLK.
23 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
22:12 TFTSTART 0x000 RW TFT Direct Drive Transaction Start
Sets the starting position of the External Direct Drive Transaction relative to the DCLK inactive edge.
11 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
10:0 DCLKPERIOD 0x000 RW TFT Direct Drive Transaction (EBI_DCLK) Period
Sets the Direct Drive transaction (EBI_DCLK) period in internal cycles. Set to required cycle count minus 1.
14.5.32 EBI_TFTPOLARITY - TFT Polarity Register
Offset Bit Position
0x07C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
Reset
0 0 0 0 0
Access
RW RW RW RW RW
Name
VSYNCPOL HSYNCPOL
DATAENPOL
DCLKPOL
CSPOL
Bit Name Reset Access Description
31:5 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
4 VSYNCPOL 0 RW VSYNC Polarity
Sets the polarity of the EBI_VSYNC line.
Value Mode Description
0 ACTIVELOW VSYNC is active low.
1 ACTIVEHIGH VSYNC is active high.
3 HSYNCPOL 0 RW Address Latch Polarity
Sets the polarity of the EBI_HSYNC line.
Value Mode Description
0 ACTIVELOW HSYNC is active low.