User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 224
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Bit Name Reset Access Description
30 PAGEMODE 0 RW Page Mode Access Enable
Enables or disables page mode reads.
29 PREFETCH 0 RW Prefetch Enable
Enables or disables prefetching of data from sequential address.
28 HALFRE 0 RW Half Cycle REn Strobe Duration Enable
Enables or disables half cycle duration of the REn strobe in the last RDSTRB cycle.
27:18 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
17:16 RDHOLD 0x3 RW Read Hold Time
Sets the number of cycles CSn is held active after the REn is deasserted. This interval is used for bus turnaround.
15:14 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
13:8 RDSTRB 0x3F RW Read Strobe Time
Sets the number of cycles the REn is held active. After the specified number of cycles, data is read. If set to 0, 1 cycle is inserted by HW.
7:2 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
1:0 RDSETUP 0x3 RW Read Setup Time
Sets the number of cycles the address setup before REn is asserted.
14.5.17 EBI_WRTIMING3 - Write Timing Register 3
Offset Bit Position
0x040
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0x3
0x3F
0x3
Access
RW
RW
RW
RW
RW
Name
WBUFDIS
HALFWE
WRHOLD
WRSTRB
WRSETUP
Bit Name Reset Access Description
31:30 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
29 WBUFDIS 0 RW Write Buffer Disable
Enables or disables the write buffer.
28 HALFWE 0 RW Half Cycle WEn Strobe Duration Enable
Enables or disables half cycle duration of the WEn strobe in the last WRSTRB cycle.
27:18 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
17:16 WRHOLD 0x3 RW Write Hold Time
Sets the number of cycles CSn is held active after the WEn is deasserted.
15:14 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
13:8 WRSTRB 0x3F RW Write Strobe Time
Sets the number of cycles the WEn is held active. If set to 0, 1 cycle is inserted by HW.
7:2 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
1:0 WRSETUP 0x3 RW Write Setup Time
Sets the number of cycles the address setup before WEn is asserted.