User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 22
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immediately on the peripheral write access. If such a write is done close to an edge on the clock of the
peripheral, the write is delayed to after the clock edge. This will introduce wait-states on the peripheral
access.
On peripherals with delayed synchronization, the SYNCBUSY registers are still present. These have two
purposes: Commands written to a peripheral with immediate synchronization are not executed before the
first peripheral clock after the write. In this period, the SYNCBUSY flag for the command register is set,
indicating that the command has not yet been performed. The second reason is backwards compatibility.
To maintain compatibility with the Gecko series, the rest of the SYNCBUSY registers are also present,
but these are always 0, indicating that register writes are always safe.
Note
If compatibility with the Gecko series is a requirement for a given application, the rules that
apply to delayed synchronization with respect to SYNCBUSY should also be followed for
the peripherals that support immediate synchronization.
5.3.1.2 Reading
When reading from a Low Energy Peripheral, the data read is synchronized regardless if it originates
in the Low Energy clock domain or core clock domain. Registers which are updated/ maintained by the
Low Energy Peripheral are read directly from the Low Energy clock domain. Registers which originate in
the core clock domain, are read from the core clock domain. See Figure 5.4 (p. 22) for an overview
of the reading operation.
Note
Writing a register and then immediately reading the new value of the register may give the
impression that the write operation is complete. This may not be the case. Please refer
to the SYNCBUSY register for correct status of the write operation to the Low Energy
Peripheral.
Figure 5.4. Read operation form Low Energy Peripherals
Register 0
Register 1
.
.
.
Register n
Synchronizer 0
Synchronizer 1
.
.
.
Synchronizer n
Register 0 Sync
Register 1 Sync
.
.
.
Register n Sync
Freeze
Core Clock
Low Frequency Clock Low Frequency Clock
Core Clock Dom ain Low Frequency Clock Domain
Low Energy
Peripheral
Main
Function
HW Status Register 0
HW Status Register 1
.
.
.
HW Status Register m
Read
Synchronizer
Read Data
5.3.2 FREEZE register
In Low Energy Peripheral with delayed synchronization there is a <module_name>_FREEZE register
(e.g. RTC_FREEZE). The register contains a bit named REGFREEZE. If precise control of the
synchronization process is required, this bit may be utilized. When REGFREEZE is set, the
synchronization process is halted allowing the software to write multiple Low Energy registers before