User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 213
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Bit Name Reset Access Description
Value Mode Description
0 D8A8 EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be
enabled on EBI_A in the EBI_ROUTE register.
1 D16A16ALE EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended
address bits can be enabled on EBI_A in the EBI_ROUTE register.
2 D8A24ALE EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended
address bits can be enabled on EBI_A in the EBI_ROUTE register.
3 D16 EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled on
EBI_A in the EBI_ROUTE register.
14.5.2 EBI_ADDRTIMING - Address Timing Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x3
0x3
Access
RW
RW
RW
Name
HALFALE
ADDRHOLD
ADDRSETUP
Bit Name Reset Access Description
31:29 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
28 HALFALE 0 RW Half Cycle ALE Strobe Duration Enable
Enables or disables half cycle duration of the ALE strobe in the last ADDRSETUP cycle.
27:10 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
9:8 ADDRHOLD 0x3 RW Address Hold Time
Sets the number of cycles the address is held after ALE is asserted.
7:2 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
1:0 ADDRSETUP 0x3 RW Address Setup Time
Sets the number of cycles the address is driven onto the ADDRDAT bus before ALE is asserted. If set to 0, 1 cycle is inserted by HW.
14.5.3 EBI_RDTIMING - Read Timing Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0x3
0x3F
0x3
Access
RW
RW
RW
RW
RW
RW
Name
PAGEMODE
PREFETCH
HALFRE
RDHOLD
RDSTRB
RDSETUP
Bit Name Reset Access Description
31 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
30 PAGEMODE 0 RW Page Mode Access Enable